It is known to use power gating transistors to control the power supply to an associated functional circuit. A control device provides a control signal to the gate terminal of the power gating transistors to control whether the transistors are on or off. When the power gating transistors are on, current passes between a power supply conductor and the functional circuit to power up the functional circuit. When the power gating transistors are off, the functional circuit is decoupled from the power supply conductor, and the functional circuit is powered down. By using the power gating transistors to cut off the power supply to a functional circuit which is not being used, power consumption can be reduced.
When the power gating transistors are first turned on, an in-rush current passes between the functional circuit and the power supply conductor. The in-rush current is the current needed to bring the functional circuit back to its powered state from a sleep or drowsy mode in which the power is off. If not controlled, then the in-rush current can be disadvantageously large. This can cause several problems. If the in-rush current is larger than can be handled by the physical limits of the design of the functional circuit, then the in-rush current arising when the functional circuit is first powered up can potentially destroy the functional circuit. Also, while the functional circuit is in a sleep mode, it is considered to be fully discharged. During the power up, the in-rush current may cause current to be drawn from other functional circuits neighbouring the functional circuit being powered up, which may reduce the voltage levels of those other circuits. To ensure that the other functional circuits operate correctly, the in-rush current should be limited.
To limit the magnitude of the in-rush current, it is conventional to provide an inverter chain on the line which supplies a control signal to the gate terminals of the power gating transistors. The chain of inverters delays the propagation of the control signal from one power gating transistor to the next, and so staggers the timing with which successive power gating transistors are turned on. Hence, fewer power gating transistors are switched on at once. By the time a later transistor switches on, an earlier transistor may have finished switching, thus smoothing the in-rush current over a longer period to reduce the magnitude of the peak in-rush current.
However, the chain of inverters requires additional gates to be added to the circuit. The inverters are always on and are connected between the high and low voltage supply rails, and so pass a large amount of leakage current. The leakage current increases the power consumption of the integrated circuit. Hence, the provision of an inverter chain reduces the extent to which power gating can reduce the power consumption of the integrated circuit. The present technique seeks to provide a way of limiting the magnitude of the in-rush current in a way that reduces the amount of leakage current.